This article is a guide for anyone interested in using machine learning frameworks in their organization.
Witam zlecę wykonanie projektu generatora obrazów testowych dla monitora na płytkę fpga Spartan, z wykorzystaniem procesora picoBlaze materiały pomocnicze podeślę na maila więcej info na maila scrollock99@
Zlecenie polega na uproszczeniu projektu demonstracyjnego w Quartusie 9.1. Należy usunąć zbędne elementy oraz okomentować kod. Proszę licytować koszt wykonania tych czynności, w komentarzu dodatkowo proszę podać cenę "konsultacji" za godzinę.
I have created the following project below. However it is too basic for a final year project, I need a larger scope for this project. Please provide any help . The alarm system is to be applied on 3 windows and a door. Each window and the door has a sensor (switch) such that when it is opened, it will give logic level 1. There is an on/off switch for the alarm which will be represented by the variable Y . If we want to turn on the alarm, the switch will give logic level 1. Otherwise, it will give logic level 0. The alarm system will be using a 7 segment display. When the system is active, the display will show character A. When it is closed , the display will show character 0. The switches below will be connected to each sensor output. • sw – window 0 • sw – ...
Accelerate python code using Vivado HLS on PYNQ FPGA
Implementar, simular FFT en entorno aldec , bajo la plataforma Atlys Spartan-6. Simular e implementar FFT en dicha plataforma, desarrollar código VHDL y detallar minuciosamente paso a paso, tomar captures y realizar documento de word detallando cada paso la oferta es de 90 usdt. Se cuenta con la tarjeta en físico por lo cual se ofrece conexión remota
We have a zedboard code which takes data from external adc and transfer over ethernet to pc. Everything is working fine. After data acquisition, we are transferring data of around 75k samples of 16 bit each to PC. Its taking around 3 min for transfer. Need work on data transfer rate and improve the same.
Need to convert MATLAB code to synthesizable VHDL code. I am using DE2 FPGA board for testing
I need a bitstream and a Linux-adapted mining software for my JungleCat with VU35P from Xillien. Freelancer will provide Bitstream and I will test its hash rate and stability. A board can also be provided for testing. Also, I need long-term support. Also write the word VCU at the end of the offer.
We are looking for someone that has deep experience in programming FPGA for RF instances. We have a need to send and receive over 30mbps and hoping to find someone with some experience in this and can guide us through a PRACTICAL code or system they built or better yet give us some learning tutorials with what they have built.
We are looking an expert over crosslink-NX to support design for a camera aggregator. We would like to hear from you, skills and experience with other projects.
We are looking for an expert over crosslink-NX to support the design of a camera aggregator. We would like to hear from you, about your skills and experience with other projects. please describe your recent experience with similar projects
Hi Harish Kumar,I noticed your profile and would like to offer you my project. The requirement for my project is to build a Cryptoprocessor using RISC -V Architecture on Vivaldo. We would be running a lightweight Cipher used in EV control unit (EV-ECU) . Aim is to carry out additional customization of instructi...(EV-ECU) . Aim is to carry out additional customization of instruction of Chiper, inject errors and collect data. Thereafter analyse the data obtained using AI-ML and be able to predict the type of error. The first stage is to Create the Cryptoprocessor on Vivaldo. I have found a research topic that guides on the same. . Need your guidance and help in this regard. We can discuss any details over chat.
Hi ePlatinum, I noticed your profile and would like to offer you my project. The requirement for my project is to build a Cryptoprocessor using RISC -V Architecture on Vivaldo. We would be running a lightweight Cipher used in EV control unit (EV-ECU) . Aim is to carry out additional customization of instructio...(EV-ECU) . Aim is to carry out additional customization of instruction of Chiper, inject errors and collect data. Thereafter analyse the data obtained using AI-ML and be able to predict the type of error. The first stage is to Create the Cryptoprocessor on Vivaldo. I have found a research topic that guides on the same. . Need your guidance and help in this regard. We can discuss any details over chat.
Need an expert using Vivado High Level Synthesis using C
- write Verilog code for steganography algorithm so that I can be implemented on FPGA - using Verilog Xilinx ise have to write module code & test bench where it can be implemented on Fpga
I am looking for an FPGA (Verilog) expert who can help me to troubleshoot and implement the EdDSA algorithm in Xilinx Vivado Design Suite. The Vivado project file is available in the attachments and several modules of the project are already completed. Looking for an expert who can do it in 3 to 4 days. Further information will be provided in the discussion.
I would like to learn more about Hardware to prepare myself to work with the development of device drivers for more complex hardware. I need someone with knowledge and/or work experience of either projecting hardware -- especially within the PCI/PCIe realm -- or developing device drivers for this kind of hardware. 1) The hardware basics: Interrupts, DMA, DRAM/SRAM(&caching), multicore & multithreading, etc - under the hoods (I know what they are, I need to understand how they work and how they interact with each other - i.e. how cpu is selected to process an interrupt). Schematics - basic notions for reading schematics, hardware documentation, etc. 2) RTL: key concepts and definitions. How and what to study about them. Where to find information. Brief introduction. 3) FPGAs: key ...
Using Pynq Z2 FPGA to connect a camera (OV7670 - CMOS Sensor), and then display the video on a monitor through HDMI output. The Project is built using VHDL language and IP blocks. The purpose of this it's to build also nurual network to recognize a face/person so the camera can follow the object using servo motor.
...have an internal project for 5G RAN FPGA design for DFE products: Skills: Job Description- Senior MTS RTL design 5G Product( 2 positions) · Candidate must have at least Bachelors or Masters EE - FPGA design experience (RTL Coding, comms, DFE(DPD, DUC, DDC, FFT, FIR, CFR) · Candidate must have verifiable experience for a minimum 6 years as a Verilog/System Verilog/ VHDL/RTL programmer with extensive Verification test bench development experience · Preferred prior project experience in 5G ORAN - RU/DU. DSP knowledge Matlab modeling is preferred. · eCPRI experience preferred . Special consideration will be given to those who have experience as 100G Ethernet or 10G Ethernet , IEEE 1588 · Knowledge of Queuing theory · Tools &nd...
A presença de erros em dados digitais é um problema frequente em sistemas computacionais que lidam com transmissão e armazenamento de informação. Em alguns contextos, como o de computação aproximada, admite-se uma taxa ainda maior de erros para alcançar uma redução no consumo de energia. Nesses casos, torna-se imprescindível o controle de erros. Isto pode ser feito através do uso d...através do uso de códigos detectores (e corretores) de erros, que são capazes de detectar (e corrigir) a informação corrompida através de redundância inserida nos dados. Nesse projeto, o objetivo é gerar um codificador baseado em paridade e um detector de erros que avisa qu...
I need to design a Hilbert transform and test it in Matlab before implementing it on FPGA. I have never created a Hilbert transform with Matlab without the hilbert() function, and the function does not return coefficients. I can't find the documentation on how to do it. I need someone to help with it. The Matlab code must also use the filter on sample data and return complex values after the transform. You should provide the Matlab code used to create the filter and get the coefficients. I will pay $70 USD for the task.
Hi Ahmed M., I noticed your profile and would like to offer you my project. We can discuss any details over chat.
Hello, I need a Lattice FPGA specialist to review my simple LCMX02 Lattice PLD design. I can not make it work, and some help is needed to understand why the PLD does not respond to the JTAG file. This is a very specific project, specifically for Lattice FPGA. I designed with other types of FPGA, and got stuck when I switched to Lattice family of parts. Thank you!
code for SPI master to send data to a GPU. project setup for the customer's terasic FPGA board. assignment. demonstration of contents via zoom meeting. I will try to complete the project before the specified end date.
Hi Islam Muhammad S., I noticed your profile and would like to offer you my project. We can discuss any details over chat.
Hi Islam Muhammad S., I noticed your profile and would like to offer you my project. We can discuss any details over chat.
Creating 2-chain Arbiter PUF on specific FPGA with 64-stages MUX for each chain. The output response PUF will be sent to external device, i.e. Arduino (microcontroller). On the other words, the output response PUF will be processed further on Arduino/microcontroller device
It is required to generate arbitrary signals in FPGA for Real Time Controls using Servo Proportional Valve with Control signals of ( +/- 10 VDC ). The various types of other signal generation in FPGA besides Arbitrary signal can be Square, Sine, Triangular. Generation of white noise signal for Real time control is also required.
Need help with code and set up for SPI protocol to send data from an FPGA to a GPU, explain code/software procedure and wiring. can forward technical specs for both devices to be used
Hi Islam Muhammad S., I noticed your profile and would like to offer you my project.
A complete color sorter Machine Firmware needs to be converted into Intel Quartus Project, The project contains IP Cores as well as softcore processor and the verilog coding part, All these to be integrated as a single bit file and to be implemented it on a Cyclone V FPGA Board.
Hi. Attached a few spike from scope capture. Need at least 8 channels simultaniously. 1. how to get detect these with a precision of 1mV? 2. how to get the value in stm32? (worked with these a lot) (or do we need an fpga) Freq is 200hz at first. Looking to get to 1 khz in the near future. Duration of the spike is only 5 to 12 microseconds. What is the best way to do this precisely ? heard tons of ideas (peak-detect circuit, 20 msps adc, etc ) , but need real proven experience. !!! please apply only if done this succefully. In the opening bid propose direclty your solution. Biggest bids will be disqualified. Stop bidding the top of freelancers brackets. No B*****S approach. Will be paid only if it WORKS! Need STM32 code, parts id, and pcb design.
The project requires an Embedded Programmer having experience in Driver Programming for FPGA cards, PCIe Interface and YOCTO as well as upbringing the Linux OS. Please DO NOT APPLY, if you DO NOT HAVE THE REQUIRED EXPERIENCE.
I need a survey paper based on 3 articles at your choose from with publication date more recent then 2010. The articles has to be based on one topic from the following. Theme variants: A. Digital signal processor architectures (e.g .: DSP, ...recent then 2010. The articles has to be based on one topic from the following. Theme variants: A. Digital signal processor architectures (e.g .: DSP, VLIW, etc.) B. Micro-architectures optimized for digital signal processing (e.g., multi-port memory, SIMD register banks, multi-core, multi-threading, etc.) C. Accelerators for digital signal processing (rapid deployments / energy efficient with FPGA, GPU, etc.) The paper must be written in latex format. 4 pages, 3-4 figures (explained) and also some references from other articles.
...sent) and get quotes from them. I will provide an email you can use to email each vendor. I have also provided a link to the item. They can’t be any random emails. I need screenshots of the company’s website and the contact information for each company. Item: FPGA STRATIX 10 2912FBGA (1SX250HH2F55E2VG) Part Link: Hello, my name is Edwin Mendez. I am writing this email on behalf of my company. We are looking for a particular part. The part that we are searching for is the FPGA STRATIX 10 2912FBGA (1SX250HH2F55E2VG). We need three of these parts ASAP. It would be great if you can provide us with this particular part. We are ready for any deal regarding the price structure. We can also schedule a meeting for any further discussions.