Verilog / VHDL - Projekty i Konkursy

Verilog is a description language used in the field of semiconductor and electronic design. It is also used in analog and mixed-signal circuits. VHDL is a hardware description language used in electronic design automation and integrated circuits. If your business is working with Verilog / VHDL then you can use some freelancer help to ease the workload. Post your Verilog/VHDL job today to connect with such freelancers.
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Przeglądaj oferty pracy na Freelancerze

Projekt/Konkurs Opis Oferty/Zgłoszenia Umiejętności Data Publikacji Kończy się Cena (PLN)
Trigger Design for FMCJESDADC1 Discuss with me to get more details on this task. Only person who has worked on FMCJESDADC1 should bid. 2 Verilog / VHDL, FPGA Dec 17, 2017 Dziś6d 9g zł803
Simple Verilog code Write a simple verilog code to create dynamic lighting using led. see the attached files and respond 21 Programowanie C, Verilog / VHDL, Mikrokontroler, LabVIEW, FPGA Dec 15, 2017 Dec 15, 20174d 3g zł453
help me with modify some Verilog code know Verilog code, how how to use Quartus and FPGA board. 14 Verilog / VHDL, Mikrokontroler, Inżynieria elektryczna , LabVIEW, FPGA Dec 15, 2017 Dec 15, 20173d 17g zł89
Program a microcontroller need you to program a micro controller as per my requirement 18 Elektronika, Verilog / VHDL, Mikrokontroler, Inżynieria elektryczna , Arduino Dec 14, 2017 Dec 14, 20173d 4g zł76
Project for Loi L. Hi Loi L., I noticed your profile and would like to offer you my project. We can discuss any details over chat. 3 Elektronika, Verilog / VHDL, Inżynieria elektryczna , , Projektowanie cyfrowe, Projektowanie obwodów elektrycznych Dec 14, 2017 Dec 14, 20175d 21g zł382
Implement a 16-bit CORDIC Computer It is to Implement a 16-bit CORDIC Computer. The design to be implemented is based on a bit-serial configuration. It will take as input a 16-bit signed binary fixed point number, corresponding to an angle in the range 0 to Ï€/2, and use the CORDIC method to find the sine and cosine of this angle. This will be coded in Verilog and implemented on the Basis 3 board. 3 Verilog / VHDL Dec 14, 2017 Dec 14, 20172d 16g zł606
Simulink design of maximum power point algorithm with DC-DC Converter I want to hire a person which having the knowledge of matlab and simulink, and design the mppt algorithm associated with my idea. Also the person should have the knowledge of electrical like DC-DC converter, basic concept of solar cell, maximum power point algorithm. 22 Inżynieria, Elektronika, Matlab i Mathematica, Verilog / VHDL, Inżynieria elektryczna Dec 14, 2017 Dec 14, 20172d 15g zł496
Multiprocessor Scheduling in c++ -- 2 - 13/12/2017 14:32 EST -- 2 Inroduction: This project is about designing and simulating a clock-driven quad-processor scheduler in an object-oriented manner. The scheduler consists of a multi-level job queue where each level follows a different scheduling algorithm viz. Priority, Shortest Job First (SJF) and First-come-first-serve (FCFS). These queues will be enqueued with PCBs. The PCBs can further be classified into Rec... 5 Programowanie C, Elektronika, Verilog / VHDL, Mikrokontroler, Inżynieria elektryczna Dec 13, 2017 Dec 13, 20172d 5g zł75
communication using simulink blocks update file of one user to five user 9 Inżynieria, Elektronika, Matlab i Mathematica, Verilog / VHDL, Inżynieria elektryczna Dec 12, 2017 Dec 12, 20171d 8g zł442
robust control project design a control system using matlab or simulink 15 Inżynieria, Elektronika, Matlab i Mathematica, Verilog / VHDL, Inżynieria elektryczna Dec 12, 2017 Dec 12, 20171d 3g zł166
model in simulink i have model for one user i want update to 5 user and get some results 10 Inżynieria, Matlab i Mathematica, Verilog / VHDL, Inżynieria mechaniczna, Inżynieria elektryczna Dec 12, 2017 Dec 12, 20171d 2g zł1338
little project about emitter follower (manually and simulated) -- 2 - 11/12/2017 21:32 EST Help me to design the circuit attatched and find out the unkown parameters both 20 Inżynieria, Elektronika, Verilog / VHDL, Mikrokontroler, Inżynieria elektryczna Dec 11, 2017 Dec 11, 201712g 10m zł118
Analogue & Digital Electronic Please, see the attached file. Analysis and design combinational and sequential digital logic, modeling concurrent digital systems using VHDL and Analogue filter. 18 Inżynieria, Elektronika, Matlab i Mathematica, Verilog / VHDL, Inżynieria elektryczna Dec 11, 2017 Dec 11, 20177g 5m zł726
multisim function generator hi i want someone to connect the function generator and the scope in multisim of electric circuit thank you 9 Inżynieria, Elektronika, Verilog / VHDL, Inżynieria elektryczna , Projektowanie obwodów elektrycznych Dec 11, 2017 Dec 11, 20176g 27m zł82
Simulink to VHDL I have done a controller for a battery energy storage system using Matlab Simulink. I need to generate VHDL codes for my controller. If you have NOT done that, please do not wast my time. 5 Elektronika, Matlab i Mathematica, Verilog / VHDL, Inżynieria elektryczna , FPGA Dec 11, 2017 Dec 11, 2017Kończące się zł82
Microprocessor Project using CodeWarrior Software Hi, Need the completed project in 36 hours. Share the codes in 24 hours and the report in 36 hours. Project details are attached here. Sample codes are attached in the files. You need to use the similar codes for the work 3 Inżynieria, Elektronika, Verilog / VHDL, Mikrokontroler, Inżynieria elektryczna Dec 11, 2017 Dec 11, 2017Zakończone zł357
VHDL to Verilog Translation I have .vhdl files for an implementation of google chrome's 'dino run' which appears when the user has no wifi connection. However, I would like to have the same functionality with Verilog description language. 9 Verilog / VHDL Dec 10, 2017 Dec 10, 2017Zakończone zł428
simulation/ VHDL Expert Needed -- Urgent job -- b I need a simulation/ VHDL expert for my current project. If you have knowledge please bid. Details will be shared in message with the selected freelancers. 7 Inżynieria, Elektronika, Verilog / VHDL, Inżynieria elektryczna , FPGA Dec 9, 2017 Dec 9, 2017Zakończone zł196
simulation/ VHDL Expert Needed -- Urgent job -- 3 I need a simulation/ VHDL expert for my current project. If you have knowledge please bid. Details will be shared in message with the selected freelancers. 3 Inżynieria, Elektronika, Verilog / VHDL, Inżynieria elektryczna Dec 9, 2017 Dec 9, 2017Zakończone zł162
simulation/ VHDL Expert Needed -- Urgent job I need a simulation/ VHDL expert for my current project. If you have knowledge please bid. Details will be shared in message with the selected freelancers. 2 Inżynieria, Elektronika, Verilog / VHDL, Inżynieria elektryczna Dec 9, 2017 Dec 9, 2017Zakończone zł126
simulation/ VHDL Expert Needed -- Urgent job -- 2 I need a simulation/ VHDL expert for my current project. If you have knowledge please bid. Details will be shared in message with the selected freelancers. 2 Inżynieria, Elektronika, Verilog / VHDL, Inżynieria elektryczna Dec 9, 2017 Dec 9, 2017Zakończone zł126
simulation/ VHDL Expert Needed -- Urgent job I need a simulation/ VHDL expert for my current project. If you have knowledge please bid. Details will be shared in message with the selected freelancers. 0 Inżynieria, Elektronika, Verilog / VHDL, Inżynieria elektryczna , FPGA Dec 9, 2017 Dec 9, 2017Zakończone -
simulation/ VHDL Expert Needed -- 2 I need a simulation/ VHDL expert for my current project. If you have knowledge please bid. Details will be shared in message with the selected freelancers. 4 Inżynieria, Elektronika, Matlab i Mathematica, Verilog / VHDL, Inżynieria elektryczna Dec 9, 2017 Dec 9, 2017Zakończone zł121
simulation/ VHDL Expert Needed I need a simulation/ VHDL expert for my current project. If you have knowledge please bid. Details will be shared in message with the selected freelancers. 7 Inżynieria, Elektronika, Matlab i Mathematica, Verilog / VHDL, Inżynieria elektryczna Dec 9, 2017 Dec 9, 2017Zakończone zł137
DDR SD ram controller DESIGN AND TEST OF A DDR SDRAM INTERFACE FOR FPGA SYSTEMS Integrate and generate the IP core of DDR, then configure that IP Core, with DCM, PLL, FIFO, and some memory interface with State machine, possible to show the output of writing and reading the data,. with report of Area, power and delay,. Simulation in any standard simulator , Xilinx/Actel/libero 11 Elektronika, Verilog / VHDL, Mikrokontroler, Inżynieria elektryczna , FPGA Dec 8, 2017 Dec 8, 2017Zakończone zł1595
FPGA Implementation of FIR filter 1. FIR design and simultion in Matlab. 2. Implement in FPGA(Xilinx Virtex-6 LX240T) and inter-connect with other logic blocks. 3. define registers for FIR filter and gain setting such that user can download filter co-efficients and gain settings through software to FPGA. 24 Matlab i Mathematica, Verilog / VHDL, Inżynieria elektryczna , FPGA Dec 7, 2017 Dec 7, 2017Zakończone zł2803
need help with missile command game on de2-115 does anyone experienced with verilog have de2-115 I need help displaying a sprite on the screen. I have all the files. 4 Verilog / VHDL Dec 5, 2017 Dec 5, 2017Zakończone zł453
Expert in Xilinx (VHDL-BASED) An efficient Glitch power reduction using sequential clock gating in VLSI circuits 8 Verilog / VHDL Dec 5, 2017 Dec 5, 2017Zakończone zł578
Project for SqUa11 -- 2 3x3 Systolic array matrix using rom and ram 2 Inżynieria, Elektronika, Matlab i Mathematica, Verilog / VHDL, Inżynieria elektryczna , Dec 4, 2017 Dec 4, 2017Zakończone zł43
Embedded systems Develop a minimal system that contains a PC, a microprocessor board, and an FPGA board. With this system, a PC application allows a user to “awaken” (or “start up”) the FPGA board through the microprocessor board. Once (and only after) the FPGA board is awakened, it waits for a push button action. After the button is pushed, it sends an 8-bit value in bit-serial to the... 9 Elektronika, Verilog / VHDL, Mikrokontroler, Architektura oprogramowania, Arduino Dec 4, 2017 Dec 4, 2017Zakończone zł150
Implementation of 32-bit MIPS Processor I need someone who knows MIPS Assembly Language and knows how to use the LogicWorks software to design a Single-cycle processor (see Figure 1 in attached document) and a Five-stage pipelined processor (see Figure 2 in attached document). Please keep all bids within the budget, otherwise you will not be selected for the project. 7 Programowanie C, Verilog / VHDL, Architektura oprogramowania, Asembler, Asembler x86/x64 Dec 4, 2017 Dec 4, 2017Zakończone zł417
Write an article about UVM (universal verification methodology) Dear ASIC Verification Experts, I am looking for ghost writer who is from ASIC verification background. I want a unique article which tries to explain why we need to use UVM. The title of the article will be similar as this. "If SystemVerilog is so good, why do we need the UVM? " The article needed to be original and meaningful content. Please bid with your experience in ASIC ver... 26 Verilog / VHDL, Pisanie artykułów technicznych Dec 4, 2017 Dec 4, 2017Zakończone zł350
putty language i need someone who can do putty and verilog 7 Inżynieria, Verilog / VHDL, Inżynieria elektryczna , Asembler Dec 4, 2017 Dec 4, 2017Zakończone zł396
Verilog Work I need some work done in verilog using Quartus 2 version 13 12 Verilog / VHDL Dec 3, 2017 Dec 3, 2017Zakończone zł517
putty coding language need an electrical engineer or computer engineer with background in putty language coding 3 Verilog / VHDL, Inżynieria elektryczna , Kodowanie, Programowanie Dec 3, 2017 Dec 3, 2017Zakończone zł100
Need a Cadence design to design a amplifier circuit. Need a Cadence design to design a amplifier circuit. details will be share in chat box. 21 Inżynieria, Elektronika, Verilog / VHDL, Inżynieria elektryczna , Projektowanie obwodów elektrycznych Dec 3, 2017 Dec 3, 2017Zakończone zł89
Design of MIPS Datapath components Using Logisim Course: Computer Organization and Architecture Project: Design of MIPS Datapath components Using Logisim Objectives After completing this project you will: · Design a 32x 32 bit register file · Design a 32 bit arithmetic and logic unit (ALU) Register File The register file consists of 32 x 32-bit registers and has the following interface as shown in Figure 1: _ BusA and BusB... 10 Inżynieria, Elektronika, Verilog / VHDL, Projektowanie obwodów elektrycznych, FPGA Dec 2, 2017 Dec 2, 2017Zakończone zł161
MATLAB code- a bit-serial CORDIC computer in Verilog MATLAB code a bit-serial CORDIC computer in Verilog to compute the sine and cosine of an angle θ. I will share the additional details later 15 Matlab i Mathematica, Verilog / VHDL Dec 2, 2017 Dec 2, 2017Zakończone zł221
Digital Design with Logic Devices It is a Project on Digital Design with Programmable Logic Devices. I will provide details later. 10 Verilog / VHDL Dec 1, 2017 Dec 1, 2017Zakończone zł186
pls help ac homewokr :'( i need log synchronous sequential circuit that solves a 64x64 maze using the right wall follower algorithm. how much???? u have 3 hours 8 Inżynieria, Elektronika, Matlab i Mathematica, Verilog / VHDL, Inżynieria elektryczna Dec 1, 2017 Dec 1, 2017Zakończone zł296
Project for Gabriel G. Hi Gabriel! I'm working on my capsim simulation final and I got myself into a lot of debt and don't know how to fix it . I need a 70% on this and was wondering if you'd be able to help. Im currently on the 3rd round of 4. Would you be able to help me out? You were suggested by a classmate and was wondering if you'd be able to help me even though I already am on round 3. Thank... 2 Zarządzanie projektem, Telemarketing, Excel, Matlab i Mathematica, Verilog / VHDL, Dec 1, 2017 Dec 1, 2017Zakończone zł524
design and implementation of a MIPS CPU with Multi cycle Data path design and implementation of a MIPS CPU with Multi cycle Data path using the VHDL language 14 Programowanie C, Verilog / VHDL, Programowanie w C++, Asembler, FPGA Nov 30, 2017 Nov 30, 2017Zakończone zł560
bubble level project the project must be developed in verilog to be executed on the Nexys4DDR ™ FPGA Board. In the video attached in the .zip, the operation of the project 8 Verilog / VHDL, FPGA Nov 29, 2017 Nov 29, 2017Zakończone zł296
VHDL code for Pipe lined MIPS-RISC (5 stage) processor.(Code for Un-pipelined will be given) I need you to do pipelining for the MIPS-RISC (5 stage) Processor. I will give you the MIPS processor code, all you need to do is pipelining. I will upload the file once go through it. If you are interested, I will send you the code and question for which code has written.” Deadline is " Dec-03-2017 " 12 Programowanie C, Inżynieria, Verilog / VHDL, FPGA, Przetwarzanie Równoległe Nov 29, 2017 Nov 29, 2017Zakończone zł614
logic analyiser and waveform viewer The data collection is done on the FPGA board. A microprocessor gets data from the FPGA board and sends data to the PC through either a Bluetooth modem or a USB port. The system supports one analog channel and one digital channel, with a single-level triggering. Only 8 bits of precision will be used for the analog channel. •Phase 1: Develop a minimal system that contains a PC, a microproce... 6 Elektronika, Verilog / VHDL, Mikrokontroler, Architektura oprogramowania, Arduino Nov 27, 2017 Nov 27, 2017Zakończone zł1149
interface hardware module with amber processor -- 2 - 27/11/2017 11:51 EST to implement an interface hardware module with amber processor 2 Verilog / VHDL Nov 27, 2017 Nov 27, 2017Zakończone zł753
Network traffic processing using two FPGAs I want to get throughput and latency results of network traffic(Ethernet packets processing) using two FPGAs, while i have throughput and latency results of using one FPGA, so i want to compare both these results. The results of using two FPGA chips should be better than using one FPGA. 6 Inżynieria, Verilog / VHDL, Inżynieria elektryczna , Administracja sieci, FPGA Nov 26, 2017 Nov 26, 2017Zakończone zł2408
C++ based project - open to bidding cpp dependencies sorting out, we will provide you the structured file and the source code and you have to compile and run after sorting mugs from that 16 Elektronika, Verilog / VHDL, Programowanie w C++, Arduino, RTOS Nov 25, 2017 Nov 25, 2017Zakończone zł385
Design and test a VHDL model for the instruction cache of a speculative out of order VLIW processor. Design and test a VHDL model for the instruction cache of a speculative out-of-order VLIW processor. Your VHDL code should have the following: - PC register updated on falling_edge of the clk to one of the following values: PC + VLIW_INST_SIZE, branch_target_PC, or EXCEPTION_ROUTINE_PC. PC register should be initialized to 1000 Hex when reset is active. Assume that the project ISA requires EXCE... 3 Verilog / VHDL Nov 25, 2017 Nov 25, 2017Zakończone zł1288
System verilog - open to bidding I need a task to be completed on system verilog, please confirm if you can do. ThanksI need a task to be completed on system verilog, please confirm if you can do. ThanksI need a task to be completed on system verilog, please confirm if you can do. ThanksI need a task to be completed on system verilog, please confirm if you can do. Thanks 10 Programowanie C, Verilog / VHDL, Programowanie w C#, Programowanie w C++, FPGA Nov 23, 2017 Nov 23, 2017Zakończone zł38
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