Verilog / VHDL - Projekty i Konkursy

Verilog is a description language used in the field of semiconductor and electronic design. It is also used in analog and mixed-signal circuits. VHDL is a hardware description language used in electronic design automation and integrated circuits. If your business is working with Verilog / VHDL then you can use some freelancer help to ease the workload. Post your Verilog/VHDL job today to connect with such freelancers.
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Projekt/Konkurs Opis Oferty/Zgłoszenia Umiejętności Data Publikacji Kończy się Cena (PLN)
VHDL Radio Clock + python script Need help in VHDL everything is mentioned on the PDF 6 Elektronika, Verilog / VHDL, Testowanie oprogramowania, Inżynieria elektryczna , FPGA Oct 19, 2017 Dziś6d 11g zł255
Project for Gabriel G. I need help with capsim practice rounds 4 Zarządzanie projektem, Telemarketing, Excel, Matlab i Mathematica, Verilog / VHDL Oct 18, 2017 Dziś6d zł89
verilog project making verilog on quartus II (cyclone IV) 11 Inżynieria, Verilog / VHDL, Architektura oprogramowania, Asembler, FPGA Oct 18, 2017 Oct 18, 20175d 18g zł526
Cloudsim project I want someone to work on programming part in cloudsim that includes migration, Placement, scheduling and power consumption. 2 Programowanie C, Java, Verilog / VHDL, Architektura oprogramowania, Programowanie w C++ Oct 18, 2017 Oct 18, 20175d 7g zł219
Verilog programming - 18/10/2017 00:34 EDT Simple verilog programming project. Create an ALU with full [adres URL ukryty - zaloguj się, aby zobaczyć] is desired is a Verilog system that can operate as a calculator with a set of logic gates attached. Other details provided later. 10 Verilog / VHDL Oct 18, 2017 Oct 18, 20175d 6g zł307
Verification Of Motion Estimator Using UVM Verification Of Motion Estimator Using UVM(Universal Verification Methodology) 3 Verilog / VHDL, Inżynieria elektryczna , Very-large-scale integration (VLSI) Oct 17, 2017 Oct 17, 20175d 5g zł826
Verilog programming Simple verilog programming project. Create an ALU with full [adres URL ukryty - zaloguj się, aby zobaczyć] is desired is a Verilog system that can operate as a calculator with a set of logic gates attached. Other details provided later. 5 Verilog / VHDL Oct 17, 2017 Oct 17, 20175d 2g zł318
ASIC Design in Verilog This project is related to Computational Neural Networks 2 Matlab i Mathematica, Verilog / VHDL, Neural Networks Oct 17, 2017 Oct 17, 20174d 22g zł315
VHDL Radio clock everything is going to be explained on the pdf 11 Elektronika, Verilog / VHDL, Mikrokontroler, Inżynieria elektryczna , FPGA Oct 17, 2017 Oct 17, 20174d 21g zł141
Design of audio visualiser using DE2-115 Altera board I want to implement an audio visualizer on the screen of the voice spoken through the mic or played using SD card. 4 Verilog / VHDL Oct 17, 2017 Oct 17, 20174d 18g zł836
Matlab power system Simulation using Simulink -- 2 - 17/10/2017 07:15 EDT My project is about the microgrid protection. I need to simulate a simple power network system (Figure 6 in the attachment) using Simulink, For the inverter I need to make some controller that can control when the microgrid is in grid mode or islanded mode (Figure 3-5 in the attachment). It is best if I can get the result same or similar with the one that in the journa 13 Inżynieria, Elektronika, Matlab i Mathematica, Verilog / VHDL, Inżynieria elektryczna Oct 17, 2017 Oct 17, 20174d 13g zł482
Matlab power system Simulation using Simulink My project is about the microgrid protection. I need to simulate a simple power network system (Figure 6 in the attachment) using Simulink, For the inverter I need to make some controller that can control when the microgrid is in grid mode or islanded mode (Figure 3-5 in the attachment). It is best if I can get the result same or similar with the one that in the journa 10 Inżynieria, Elektronika, Matlab i Mathematica, Verilog / VHDL, Inżynieria elektryczna Oct 17, 2017 Oct 17, 20174d 11g zł563
Elektronika, Verilog / VHDL, Mikrokontroler, Inżynieria elektryczna , LabVIEW Oct 16, 2017 Oct 16, 20174d 5g
netlist construction in EE using C++ refactor the sample code by using the c++ 9 Programowanie C, Verilog / VHDL, Programowanie w C#, Inżynieria elektryczna , Programowanie w C++ Oct 16, 2017 Oct 16, 20173d 18g zł483
project for Ahmed M -- 2 - 16/10/2017 12:09 EDT I believe you must do this project. 2 Verilog / VHDL Oct 16, 2017 Oct 16, 20173d 18g zł454
project for Ahmed M I believe you must do this project. 1 Verilog / VHDL Oct 16, 2017 Oct 16, 20173d 18g zł554
verilog project want verilog code on fpga i want soon 2 Inżynieria, Verilog / VHDL, Architektura oprogramowania, LabVIEW, FPGA Oct 16, 2017 Oct 16, 20173d 17g zł29
ASIC Designs and Development Hello. I am into a project that involves creating PCB / ASIC design with FPGA/CLPD. The specified ASIC Architecture as a product needs to be able calculate one or more algorithms connected through some type of data socket. Performance and power is important. I am interrested to get in touch with a board designer and vhdl developer that have knowledge both with electrical layouts and vhdl. ... 6 Inżynieria, Elektronika, Verilog / VHDL, Inżynieria elektryczna , Projektowanie obwodów drukowanych (PCB) Oct 16, 2017 Oct 16, 20173d 10g zł54
veriloghdl code for calculation area THis must implement on quartus( altera FPGA cyclone IV) 4 Programowanie C, Verilog / VHDL, Mikrokontroler, Programowanie w C++, FPGA Oct 16, 2017 Oct 16, 20173d 10g zł368
making verlog hdl code calculataion area in black and white image on fpga ( cyclone IV) 8 Programowanie C, Verilog / VHDL, Mikrokontroler, Inżynieria elektryczna , Programowanie w C++ Oct 16, 2017 Oct 16, 20173d 6g zł447
VHDL Coursework help in VHDL codes ,, everything will be explained later 13 Inżynieria, Elektronika, Verilog / VHDL, Inżynieria elektryczna Oct 15, 2017 Oct 15, 20172d 22g zł198
fpga software I want to read programmes in FPGA chips 17 Programowanie C, Verilog / VHDL, Architektura oprogramowania, FPGA Oct 15, 2017 Oct 15, 20172d 16g zł1477
creation of hardware module using verilog which will be able to communicate with the memory of the processor using Verilog which will be able to communicate with the memory of the processor 4 Verilog / VHDL Oct 14, 2017 Oct 14, 20171d 15g zł222
simple verilog hdl code calculate each area in black and white image 11 Programowanie C, Inżynieria, Verilog / VHDL, Mikrokontroler, FPGA Oct 13, 2017 Oct 13, 20171d 4g zł168
Simple Verilog Project Design a perception timer that measures the time for a user to respond to a request to complete a simple task. I'll send the rest details for part 3. 8 Inżynieria, Matlab i Mathematica, Verilog / VHDL, Inżynieria elektryczna , FPGA Oct 13, 2017 Oct 13, 201721g 37m zł86
Color space conversions and FPGA's 3 pages report in two parts on: (i) fundamental information about FPGAs and their programming, and (ii) standard color spaces and formulas for converting those color spaces into other ones. (Plagarism free) finished in 3 days maximum. 9 Inżynieria, Verilog / VHDL, Inżynieria elektryczna , FPGA Oct 13, 2017 Oct 13, 201711g 38m zł236
Build software Looking for expert in FPGA and verilog 18 Programowanie C, Verilog / VHDL, Architektura oprogramowania, Programowanie w C++, FPGA Oct 12, 2017 Oct 12, 2017Zakończone zł1716
Statcom in simulink Power electronics expert -- 2 Statcom in simulink Power electronics expert needed 9 Elektronika, Matlab i Mathematica, Verilog / VHDL, Inżynieria elektryczna , FPGA Oct 11, 2017 Oct 11, 2017Zakończone zł587
Want to develop robotic program and test the same with simulation to check feasibility of and automation idea Existing : Manual labours are lifting filled 25 kg bags from stack of machine palletised load (40 bags per wooden pallet, and loading into trucks, containers. Automation solution : Using three axis gantry robot, vacuum lifting end tool and smart programming to create fully automatic truck loading system. All above only on simulation, 3d models to check feasibility of solutions and then to us... 5 Matlab i Mathematica, Verilog / VHDL, Architektura oprogramowania, Tworzenie oprogramowania, Programowanie Oct 11, 2017 Oct 11, 2017Zakończone zł16732
VLSI PROJECTS FIND THE ATTACHED IEEE [adres URL ukryty - zaloguj się, aby zobaczyć] REQUIREMENTS 4 Verilog / VHDL, FPGA, Very-large-scale integration (VLSI) Oct 11, 2017 Oct 11, 2017Zakończone zł307
Statcom in simulink Power electronics expert Statcom in simulink Power electronics expert needed 9 Elektronika, Matlab i Mathematica, Verilog / VHDL, FPGA Oct 11, 2017 Oct 11, 2017Zakończone zł407
Convert a code from Aptech Gauss language into Matlab with Parallel processing. I have a code written in Aptech Gauss program that I want to convert into Matlab and I want the code to run under CUDA power in Matlab. 3 Matlab i Mathematica, Verilog / VHDL, Architektura oprogramowania, CUDA, Tworzenie oprogramowania Oct 10, 2017 Oct 10, 2017Zakończone zł546
Develop, Test and Implement it in software environment and simulate the circuit functionality - open to bidding We need to develop a digital multiplier circuit and we need to test the circuit design, Implement it in software environment and simulate the circuit functionality. This is going to be part of a bigger project (ARM IP Core, DSP CPU) and we may need to compare the circuit functionality with some other recommended multiplier in terms of speed and foot print. 7 Elektronika, Verilog / VHDL, Inżynieria elektryczna , Projektowanie cyfrowe, Projektowanie obwodów elektrycznych Oct 10, 2017 Oct 10, 2017Zakończone zł381
Prelab Write VHDL code 7 Verilog / VHDL Oct 10, 2017 Oct 10, 2017Zakończone zł97
dimensionality reduction using PCA we will consider use of PCA for simple dimensionality reduction, i.e., determining the signal subspace when there are more observations than the underlying latent variables—signals. The main assumption here is that both the noise and signals are independent and identically distributed Gaussians, however the the signals are correlated among themselves while the noise components are not, ... 14 Matlab i Mathematica, Verilog / VHDL, Analiza metodą elementów skończonych, CUDA, FPGA Oct 10, 2017 Oct 10, 2017Zakończone zł1459
ZYNQ c/ verilog project(s) There is a Zynq C/ Verilog project involving BRAM and data structures , to be done. We will start with a 50 usd small project, on successful completion we will move into larger budget projects( a few hundred USD ones) .PM me to talk the details. 11 Programowanie C, Verilog / VHDL Oct 10, 2017 Oct 10, 2017Zakończone zł293
Altera DE115 - Audio signal processing Record voice , Add and Remove Noise and play back recording. Design and implement the verilog code on an Altera DE2-115 Development Board. Available Hardware Microphones, Speakers 9 Verilog / VHDL, Mikrokontroler, Oprogramowanie wbudowane , Asembler, FPGA Oct 10, 2017 Oct 10, 2017Zakończone zł807
Audio Signal Processing AIM - Record Audio , Add and Remove Noise and play back audio. To design and implement the Embedded System centred on an Altera DE2-115 Development Board. The project should be based on a Verilog HDL implementation. Available Hardware In addition to the DE2-115 board, the following hardware devices are available. If you wish to do a project requiring hardware support but don’t see the... 7 Verilog / VHDL, Mikrokontroler, Inżynieria elektryczna , Oprogramowanie wbudowane , FPGA Oct 10, 2017 Oct 10, 2017Zakończone zł1818
Sequence Diagram There is a service class called PurchaseOrder that is called when a customer makes a purchase. It has a public method purchase(Account, Order). It does the following. a. Call [adres URL ukryty - zaloguj się, aby zobaczyć]() b. Call [adres URL ukryty - zaloguj się, aby zobaczyć](Account) c. Call [adres URL ukryty - zaloguj się, aby zobaczyć]() d. [adres URL ukryty - zaloguj się, aby zobaczyć]()... 6 Verilog / VHDL, Architektura oprogramowania, PLC oraz SCADA, Analiza metodą elementów skończonych, Rysunek techniczny Oct 10, 2017 Oct 10, 2017Zakończone zł132
Matlab Program for Harmonics Analysis for a sampled data (Data in excel format) Need a Matlab program to perform Harmonics Analysis for a sampled data (data in Excel format). Matlab Codes must structured to read data from Excel file. Please find the attached Excel file [adres URL ukryty - zaloguj się, aby zobaczyć] 22 Excel, Matlab i Mathematica, Verilog / VHDL, Architektura oprogramowania, Tworzenie oprogramowania Oct 7, 2017 Oct 7, 2017Zakończone zł78
UML/MARTE modeling I want to build an interface(which consists of rules) to transform any MML model to a UML-MARTE model using AGG(algebraic graph transformation). 1 Verilog / VHDL, Projektowanie UML, Analiza metodą elementów skończonych, SAS, CATIA Oct 7, 2017 Oct 7, 2017Zakończone zł2097
matlab report making 10 pages minimum hi discussion via chat no front milestone need it in 12 hrs 10 mages maximum paper should be in IEEE formats no plagiarism is there.. please give a good quote 10 Matlab i Mathematica, Verilog / VHDL, LaTeX, Matematyka, Fizyka Oct 7, 2017 Oct 7, 2017Zakończone zł172
Matlab Write a Function for Forward Kinematics of the RPR Robot Input Format are the joint angles in radian, as shown in the figure is the extension of the prismatic joint in inches, as shown in the figure Output Format R is a 3x3 rotation matrix representing (Note: where represents a point in frame x) pos is a 4x3 matrix where each row contains the x,y,z coordinates represented as [x y z] in matrix form. Each row is the x,y,z coordinates of a point... 16 Matlab i Mathematica, Verilog / VHDL, Architektura oprogramowania, Analiza metodą elementów skończonych, Tworzenie oprogramowania Oct 7, 2017 Oct 7, 2017Zakończone zł136
String compare algorithm need an algorithm that would compare two long strings delimited by | 3 Matlab i Mathematica, Verilog / VHDL, Algorytmy, CUDA, Uczenie maszynowe Oct 7, 2017 Oct 7, 2017Zakończone zł7008
Cryptoanalysis - Cryptograpgy - C programming I am looking for someone to write me a code in c that will test the cryptographic strength of the passwords. I can share more specific instructions and dummy passwords. I need a simple program. 9 Programowanie C, Verilog / VHDL, Architektura oprogramowania, Prolog, Programowanie w C++ Oct 6, 2017 Oct 6, 2017Zakończone zł246
MSF and DCF receiver everything will me explained later 5 Inżynieria, Elektronika, Verilog / VHDL, Inżynieria elektryczna , Analiza Binarna Oct 6, 2017 Oct 6, 2017Zakończone zł163
Embedded Control System Design It is a project on Embedded Control System Design. I will give the details later. 12 Programowanie C, Verilog / VHDL Oct 6, 2017 Oct 6, 2017Zakończone zł157
ABAQUS Model (CFRP Beam) I need to make the results of this ABAQUS model converge with the experimental data curve (shown in the Excel sheet: Load vs Deflection). The current results shows a much higher yield and peak loading compared to the experimental data. The model files are attached to this project. 13 Verilog / VHDL, Analiza metodą elementów skończonych, Grafika komputerowa, Inżynieria przemysłowa, CATIA Oct 5, 2017 Oct 5, 2017Zakończone zł676
Simulation profile need a private tutor for ANSYS-Fluent and ICEM-CFD 8 Matlab i Mathematica, Verilog / VHDL, Analiza metodą elementów skończonych, FPGA, CATIA Oct 5, 2017 Oct 5, 2017Zakończone zł576
VHDL circuits project have few questions on digital circuits that I need help with. will provide more details of interested 23 Verilog / VHDL, Projektowanie obwodów elektrycznych, Programowanie Oct 4, 2017 Oct 4, 2017Zakończone zł275
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