Design of a Downconverter / Upconverter for Xilinx FPGAs - open to bidding

Hi we contacted through Elance however I do not have a credit card and I could not proceed with contacting you. My e-mail is pieza_kake@yahoo.co.uk. Is there any other payment method we could use? I have debit master card or I could make a deposit in bank account. Also about the date I need the project done as fast as possible, in less than a week that would be. Something important: ONLY MATLAB-SIMULINK AND XILINX ISE can be used in the [login to view URL] not write any VHDL. I have attached a file with the description of the project. Also I attached an example of how the report should look like (however with improved format). In this link [login to view URL] you will find most of the staff you will need for the project along with a workbook. I also attached a file with the project that a guy I had hired made, which is a total mess. I had sent him the files of my friends project and he basically renamed some files and tried to cheat me. To run the simulation open the simulink file first then run DDC1_setup.m The total time expected to require by an experienced FPGA engineer is 30 hours. Thank you