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Future technologies will allow the integration of hundreds of billions of transistors on a single chip allowing the fabrication of chips with hundreds of processing cores. So, IC designers should focus on the communication between these cores in order to meet the design requirements in terms of speed, area, power consumption, and time to market constraints. Using conventional parallel buses to transmit data on-chip is not efficient anymore in terms of area, given that in new technologies interconnects do not scale at the same rate as transistors do, and in terms of power due to the large number of drivers, repeaters, and buffers. Also, parallel buses suffer from timing errors due to jitter, and cross talk that eventually limit the performance. One of the solutions to solve these on-chip communication issues is to replace conventional parallel buses with serial links. Many publications already proposed solutions based on serial links, and dealt with the intersymbol interference on their interconnects using equalization, frequency translation using high frequency carrier signal or using data encoding, or using resistive terminated interconnects.

In this project, the transmitter section of the SerDes device is discussed. It consists of serializer and Three Level Encoder. Serializer transmits parallel data into serial data. Then this data is passed to Three Level Encoder. Three Level Encoder maintains the DC level of the signal. It is used to embed the clock and data. Serializer is implemented with two types of techniques one is simply by using MUX and another is by using DETFF. Limitation of MUX is overcome by DETFF.

Programowanie C Elektronika Oprogramowanie wbudowane Verilog / VHDL Very-large-scale integration (VLSI)

Numer ID Projektu: #15319234

O projekcie