designing VerySimpleCPU

2) There, InstructionSet folder has the description of VerySimpleCPU instructions. Sim folder is where you may work on your assembly programming. VerilogTB is where you may work on your VerySimpleCPU.v. 3) No need for you to write a new assembly program. I have [login to view URL] in Sim folder. It tests every single instruction. It even tests some instructions under a few different conditions. After you run this program on your Verilog design, you should make sure that you see the "after =" values in the marked memory locations. Other locations do not change. A few locations may change although they should not change if your design is buggy. 4) When you run the simulator/assembler [login to view URL], it assembles your program for Verilog simulation as well. The Verilog version of the assembler output is in program.v, which is directly in Verilog syntax. 5) Copy program.v into VerilogTB folder. It is included from blram.v and programs the block RAM (memory) VerySimpleCPU with everything in the .asm file (program and input data). 6) You may then simulate your design (VerySimpleCPU.v), tb.v, and blram.v in VerilogTB folder using Xilinx ISIM (part of Xilinx ISE design suite). 7) If your design is working, meaning if you see the "after =" values in the memory locations marked in [login to view URL], then your design is possibly correct. You may also want to check your program with the recursive factorial program in Lab4. It is best if you try your design with also an assembly program you write. 8) Make sure your VerySimpleCPU.v synthesizes without any errors or warnings except #1 related warnings. Map the IO of your VerySimpleCPU to some arbitrary pins in a .ucf file.