ProjectDone
$15-25 USD / godzinę
The project is over VHDL using Vivado software, and it contains five smaller parts. have a fun with FPGA and hardware language.
Numer ID Projektu: #18193185
O projekcie
8 freelancerów złożyło ofertę na średnią kwotę $19/godzinę w tym projekcie
Dear Sir. I am very interested in your project and I would be happy to work on it. I can make the parts of your project. I am a Senior Electronic Engineer with experience in the design / development of embedded s Więcej
Am a solid independent specialist, I am so eager to function as a consultant, I am a diligent employee, inspired by meeting set focuses inside due dates, as it gives me a feeling of achievement. I focus on points of in Więcej
I have passionate about designing the digital circuit using verilog . I had design and verified the SPI communication protocol. I also work on FPGA.
I have experience with FPGA Design and VHDL science 2003. I used alters in my master 2004 and Xilinx in my PhD. 2008. I put the minimum money per hour because I want to have reviews in free lancer. best regards
I have done this type of projects and I also have prepared these kind as a teaching assistant at university. I believe I can handle this in one day, spending enough time in a day.