RS-FEC 198,194 verilog code
$30-250 USD
Płatność przy odbiorze
VLSI design for Reed Solomon FEC for 198,194 including documentation and explanation.
Verilog files and simple testbench to prove the design.
ASIC
Numer ID Projektu: #20012622
O projekcie
8 freelancerów złożyło ofertę za $110 w tym projekcie
Hi my Professional Aim is: ( Services then Solutions then Satisfactions) I hope you are good. As an experience in this field from last 5 years i am sure i can do it perfectly with in a time a Więcej
I have well experienced in doing such kind of jobs........................................................................................................................................................................ Więcej
Hello! I have briefly read the description on fec-verilog-code development project, and I can deliver as per the requirements however I need us to discuss for more clarity on the details, deadline and budget as Więcej
Hi, I have worked on Verilog, VHDL, System Verilog and have developed many complex IPs for FPGA and ASICs. I can develop this verilog code for you. Let me know whether you are looking for an encoder only. Also shar Więcej
Hello sir, i am girish Phalake, FPGA design engineer with better industry experience, i am very good at paper design and also good in english Thank you!
I have well experienced in the following topics.. Electronic circuits,Digital electronics Signals and system,Digital signal processing Digital image processing,Verilog/VHD Więcej
