(BIST) Built in self test verilog/ vhdlcode for memory

The aim of the project is to design a BIST controller to insert and detect the faults (defect) like Read disturbance, Erase disturbance, Program disturbance, SAF, TF, ADF, CFs, TF, NPSF, Retention fault in FLASH memory by using BIST algorithm like March algorithm using verilog or VHDL in Xilinx or Modelsim.

Need Simulation waveforms for the same.

Umiejętności: Inżynieria, Mikrokontroler, Verilog / VHDL

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O pracodawcy:
( 0 ocen ) Bangalore, India

Numer ID Projektu: #17806030

2 freelancerów złożyło ofertę na kwotę ₹30000 do tego projektu


Hi, I hope you are doing well and enjoying digital design. I believe implementing a design right form modeling until verifying it on an FPGA is always a very special experience. Throughout my 3+ years of experie Więcej

₹30000 INR w ciągu 5 dni
(4 Oceny)

Hello, I have expertise in ASIC/FPGA Design & Verification and worked on following languages. VHDL Verilog Systemverilog/UVM MATLAB Python Perl EDA Tools: Modelsim/Questasim Xilinx VCS Simulink I have worked on BI Więcej

₹30000 INR w ciągu 15 dni
(0 Oceny)