Fpga vivado (image processing)

Zynq Video Pipe Line Specification 1 Overview The job requires Jigarkumar (referred to as the designer) to create a real time image processing video pipeline on Zynq SoC. The details are discuss in the following sections. 2 Specifications 2.1 The designer shall help the Lumina Inova (Referred to as the Client) in building a real time processing pipeline on Zynq for the purpose of real-time image stitching. The project is broken down into milestones. 2.2 Milestone 1 – Involves the Designer building a firmware/software system (Figure 1) in Xilinx Vivado and Xilinx SDK respectively to: 2.2.1 Read 640 x 480 resolution images from an SD card, 2.2.2 Store these images into RAM (of the Enclustra ZX3 /EB1 development kit), 2.2.3 Read a Look up table (LUT)(Client shall provide this) 1750x1750 resolution from SD card and store in RAM. This space shall be accessible and reserved in the Xilinx SDK code for later use. 2.2.4 Place images side by side (Scaling might be required), 2.2.5 Output side by side images to video out IP which will go to an HDMI output. 2.2.6 Assist Client with implementation of Designers code on Enclustra. The Design shall also educate the Client on how the blocks work and explain code. 2.2.7 The Designer shall provide an empty container in C++ code (Xilinx SDK and HLS) where the Client can substitute code. Axi Timer for benchmarking. 2.3 Milestone 2 – One Milestone 1 has been achieved, 2.3.1 The SD card source will be switched to camera sources (The Client shall provide the code for camera link video IP). 2.3.2 The Camera video (640x480 resolution at 25 FPS) shall follow the same process as Milestone 1 (Sections 2.2.2 to 2.2.7). This is so that video can be viewed side by side via HDMI on an LCD monitor. 2.3.3 The Designer shall provide simple benchmarking tools so that the Client can measure performance and latency of the placing images side by side. 2.4 Code shall be optimized to take full advantage of the acceleration of Processor Logic. Necessary PRAMA directives such as line buffers and parallel processing, should be used where necessary.