Hi,
I have experience in Designing FPGA Project Xilinx/Altera and Embedded Codes for the same.
Coming to your problem statement:
Your Vivado IPI design looks good to me. I don't see any connection issues there, if any we can debug remotely.
Coming to your SDK Code, I can go through the code, and debug and provide you solutions within 2-3 Days.
Let's discuss what is the symptoms when you say "It is not working".
Thanks!