VLSI design and testability using SPICE/ Verilog/VHDL

Zamknięty Opublikowano 6 lat temu Płatność przy odbiorze
Zamknięty Płatność przy odbiorze

An applied project may involve using tools such as Spice, Verilog/VHDL, etc. to demonstrate its success

Verilog / VHDL Very-large-scale integration (VLSI)

Numer ID Projektu: #15447244

O projekcie

8 ofert Zdalny projekt Aktywny 6 lat temu

8 freelancerów złożyło ofertę za $482 w tym projekcie

ahmedmohamed85

A proposal has not yet been provided

$444 USD w ciągu 3 dni
(390 Oceny)
7.8
loi09dt1

A proposal has not yet been provided

$750 USD w ciągu 15 dni
(111 Oceny)
6.5
rubelsarkar161

Hi, I do work as a IC Layout and system design engineer in Bangladesh. Hope I can help you Or, if you need any help regarding IC layout mask design you can contact

$555 USD w ciągu 4 dni
(2 Oceny)
2.4
mze5583fac62088c

Hi Muhammad, my name is Zeeshan. Please share more details of your project. Relevant Skills and Experience I am MS Electrical Engineer and have extensive experience with Spice and verilog. Proposed Milestones $333 US Więcej

$333 USD w ciągu 10 dni
(1 Ocena)
1.9
ganewatthe

I need more information on the project task. Relevant Skills and Experience I'm familiar with verilog/verilog-a/verilog-ams and spice. Stay tuned, I'm still working on this proposal.

$333 USD w ciągu 10 dni
(0 Oceny)
0.0
elkhamlichi6m

hi sir you can hire me

$333 USD w ciągu 2 dni
(0 Oceny)
0.0
hytr21

I try my best if you give a chance ☺

$666 USD w ciągu 5 dni
(0 Oceny)
0.0