Altera DE-1 SoC

Zamknięty Opublikowano 7 lat temu Płatność przy odbiorze
Zamknięty Płatność przy odbiorze

Fixing an existing Data Transfer Project.

Verilog / VHDL

Numer ID Projektu: #13233870

O projekcie

6 ofert Zdalny projekt Aktywny 7 lat temu

6 freelancerów złożyło ofertę za $207 w tym projekcie

ahmedmohamed85

Dear sir I have more than 9 years experience in digital design using FPGA also I already have the Altera DE1 SOC board, please message me so that we can discuss

$222 USD w ciągu 3 dni
(270 Oceny)
7.5
loi09dt1

A proposal has not yet been provided

$90 USD w ciągu 3 dni
(83 Oceny)
6.2
ducdctoandh

Dear customer, I am really happy to help you out of this project. I would like to introduce that I am an freelancer with 100% JOB COMPLETED in VHDL/VERILOG. I am really suitable for job description: First: I a Więcej

$250 USD w ciągu 3 dni
(46 Oceny)
5.4
rohi1710rohi1710

Hi, -FPGA design engineer since last 7 years -Expertise in verilog/VHDL Please find below details of the projects TSMAC Hardware acceleration(3months) The project is to develop hardware acceleration block for TS Więcej

$250 USD w ciągu 3 dni
(5 Oceny)
4.6
OlektraGroup

dear Sir i can do this project. I can assure you that if you work with me once, you will always work with me for these kind of projects.

$155 USD w ciągu 3 dni
(5 Oceny)
2.6