to design I2C master on altera MAX10
$30-250 CAD
Płatność przy odbiorze
Taking reading from ADC and display it on I2C LCD on Altera MAX10. ADC should be designed using Qsys. MAX10(i2c master) is connected to i2c LCD (Slave) to display the value.
Numer ID Projektu: #12097053
O projekcie
Przyznany użytkownikowi:
4 freelancerów złożyło ofertę za $135 w tym projekcie
Dear sir I have more than 9 years experience in digital design using VHDL, please check my profile, also please message me
Hi, -FPGA design engineer since last 7 years -Expertise in verilog/VHDL Please find below details of the projects TSMAC Hardware acceleration(3months) The project is to develop hardware acceleration block for TS Więcej