Asynchronous FIFO
$10-30 USD
Płatność przy odbiorze
Need VHDL code for Asynchronous FIFO.
The design should be based on this paper:
[url removed, login to view]
Numer ID Projektu: #11869426
O projekcie
8 freelancerów złożyło ofertę za $50 w tym projekcie
I have proficiency with VHDL and Verilog. I write custom codes which will be area optimized,efficient in terms of power and frequency.
dear Sir i can do this project. I can assure you that if you work with me once, you will always work with me for these kind of projects.
- Day - 1 : 1. will go through link & read document what you have provided. 2. after discussing with you about more details will provide you a top module black box Więcej
hi you, I can complete this project around three hours, and i can send you waveform simulation next day...i have two years experience in Verilog design, Can this project completed with Verilog version? Thanks Vu
