Aya S.

Hi, my name is Aya. I am a digital design Engineer and got Bachelor's degree in electronics and communications from Nile University. here are some of my accomplishments and qualifications that will help you in your project: ■ Verilog and VHDL HDL languages ■ System Verilog ■ programming language: python/C/C++ ■ Knowledge about FPGA and ASIC design flow ■ Knowledge about principles of VLSI RTL Design: power, Static time analysis, clock domain crossing ■ Work on : vivado , ModelSim, libero, diamond tools