DDR3 Hardware(Circuit and PCB) Desginer(Virtex-7)

I have long experience with FPGA and VHDL . I work with both intel and Xilinx FPGAs , SoC and SOPC. I use Quartus II and Vivado IDEs accordingly. I test timing compliance through timing analysis . I deliver tested , neat and well-commented code that can be reused or modified for future development. More to be discussed once you contact me . BR, M.T.

Hi, answers to your questions: 1- yes multiple copies can be run in a single device 2- yes there is, a single copy can calculate for example 6Million hashes per second which translates to 6 Mega Hashes per second, two cores will run in parallel each contributing 6 MH/s to a total of 12 MH/s for the device 3- depends on the algorithm/clk freq/device ... 4- again depends on many parameters. Virtex devices have more recources in comparison to other devices from Xilinx. Kintex devices runs second. However, there is no single virtex or kintex device. The names of the devices represents the architectural intends of Xilinx. There are smaller(in terms of logic capacity) virtex devices than some bigger kintex devices. If you want the biggest device (in terms of logic capacity) most probably it is a virtex device. On the other side, those big devices of virtex comes with additional features, probably that you would never use, which costs money. best regards,

We are a young Ukrainian software development company that employs several passionate engineers. Our main direction is the engineering, development and implementation of custom software with a deep scientific focus that requires strong skills in mathematical and natural sciences. The technical leadership of the company is held by two keen scientists with Ph.D. degrees in physics, mathematics and technical sciences. During the last 5 years we have been involved in several projects related to cloud computing, math libraries, machine learning, parallel computing, CAD/CAE, engineering drawing, production costing, computer vision, remote device control, brain physics modeling, natural language processing, satellite imagery and more. We would be happy to take care of your boldest and most complicated projects!

Dear Sir, Please elaborate your project in bit detail. It will help us to serve you in more better way. It would be more easy for us to evaluate your requirement if we know details like, 1. Which FPGA/AP SOC you are using 2. Have you already completed the hardware part 3. Where are the inputs coming from. where they are fed to FPGA in use. which communication protocol is used. And other details which will cover a wider view of your system. Awaiting your kind response. Thanks and regards, Prashant

I have worked on Virtex-7, Kintex and Kintex UltraScale FPGAs. I also have working experience in DDR3 and DDR4 interfaces. I can deliver in good quality. Thanks

I have done integration/ verification/validation work for Xilinx AXI MIG7 DDR controller for 8 GB DDR ram in three weeks, identified two bugs in MIG7 DDR controller, The data bus width was 512 bytes, the implemented 7 test cases ( all ones, all zeros, walking ones, walking zeros, incremental, PRBS9 on 32 bits, custom pattern) The design then was implemented in Vivado for kintex 7 architecture , ILA and VIO support added,