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FPGA and DSP develper

min $50 USD / hour

W trakcie realizacji
Opublikowano ponad 6 lat temu

min $50 USD / hour

Looking for a developer to learn and implement a real time hardware implementation of spectrum analyzer upto 100mhz bandwidth using FPGA, fast ADCs and DACs.
Identyfikator projektu: 15661729

Informację o projekcie

10 ofert
Zdalny projekt
Aktywny 6 lat temu

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10 freelancerzy składają oferty o średniej wysokości $58 USD/godz. dla tej pracy
Awatar Użytkownika
Hi, I am a post graduate power electronics engineer and having very good experience in product design and development. I am excellent in embedded design & programming using pic, dspic controllers and MATLAB codding for Power projects, Boot loaders, Bluetooth & GPS designs,CAN communication, EEprom. UART , RF circuits ,Protocols for networking, wi-Fi routers,OBD diagnosis with CAN bus protocols, Electrical vehicles and AC drives, stepper motor controls. I designed sine wave inverters for standalone and grid tie Inverters. I designed projects like Off line UPS up to 3 KVA, synchronous rectifiers, Solar MPPT chargers, Solar trackers, Battery chargers ,Grid tie inverters design with PLL and feedback control circuit emergency light of 66W and Online UPS control cards, Battery Charging power supplies, LED drivers for PWM controlling and dimming, SMPS, Power supplies. I have experience in schematics and PCB design experience in Altium and ORCAD. I am ready to work for you. Please contact for further discussion.
$55 USD w 40 dni
4,9 (60 opinii)
6,7
6,7
Awatar Użytkownika
Dear Sir/Madam, I, on behalf of Dyumnin Technologies am submitting this proposal in response to your project for Implementing a Spectrum Analyzer on an FPGA. Dyumnin Technologies was founded in 2016 by a Semiconductor Industry professional with over 15 years of experience in Digital IP design in the field of wired and wireless communication and display technology with Industry leaders like Texas Instruments and Intel. With respect to your specific requirements I would like to propose the following steps. You can contact me over chat and we can discuss/schedule a discussion to exchange the details of the requirements. i.e. : * The algorithm that needs to be used. * The maximum frequency that needs to be captured. * The Preferred FPGA for implementation. * Any other items related to the specification of the project. Once we have a clarity on what we need. We can finalize the project schedule and intermediate milestones, and you can award the bid based on the schedule and deliverable agreement. We will start the project execution by creating a detailed Architecture, design and verification specification based on our discussions. And then start the actual Design, Coding and verification process as per the agreed schedule.
$50 USD w 40 dni
4,9 (4 opinii)
4,6
4,6
Awatar Użytkownika
I have a lot of experience on interfacing FPGA and ADC/DAC; especially Xilinx FPGA and Analog device, TI ADC/DAC.
$50 USD w 15 dni
4,8 (16 opinii)
4,8
4,8
Awatar Użytkownika
I have extensive knowledge on FPGAs and digital design with VHDL. I have successfully completed projects spanning different domains of application. Feel free to ask anything you have in mind over chat.
$70 USD w 20 dni
5,0 (6 opinii)
4,2
4,2
Awatar Użytkownika
Hi, please help me to proceed with the same.
$55 USD w 6 dni
0,0 (0 opinii)
0,0
0,0
Awatar Użytkownika
please contact me for more details.
$55 USD w 30 dni
0,0 (0 opinii)
0,0
0,0
Awatar Użytkownika
This is literally my wheelhouse. I have experience in this exact field due to being a SMPS designer. I've dealt with DSP techniques including hardware FFTs, interfacing with ADCs though not with JESB2048, but I can probably figure out LVDS based. If its at logic level or differential it is easier. Also using analog electronics to interface with the ADC can be done for instrumentation. Noise analysis, FFT/IFFT/Chirp/Hartley or other transforms, using MAC blocks or choosing between Fixed or Floating Point (Half/Single/Double/Quad) using RAM as a buffer for ADC reads, and beyond. I have experience in this. Given an FPGA with a clock source and shared PLL hopefully to the ADC I can make an SA or Vector Signal Analyzer, both with differential or single ended input options. Since there is a bandwidth limitation I can't make it with digital isolation unless a heterodyne option is added. Otherwise most Verilog implementations of the FFT are around 10 cycles or a bit more, and buffering to either fast access DRAM or SRAM would be helpful. Ideal sampling length, averaging, filtering and other mixed signal and DSP techniques can be utilized depending on power requirements or analysis accuracy.
$55 USD w 100 dni
0,0 (0 opinii)
0,0
0,0
Awatar Użytkownika
Working professional in hardware engineering and have ongoing knowledge of tools and caveats. Good coder, effective communicater, love to share and talk HDL.
$50 USD w 40 dni
0,0 (0 opinii)
2,7
2,7
Awatar Użytkownika
Hello, thank you for the opportunity to bid on your project! I'm an experienced electronics designer with numerous projects involving high speed FPGA data acquisition (mostly on Altera FPGAs, but have experience with Xilinx and Lattice as well). I recent project involved very careful and precise signal generation and capture for a new Focused Ion Beam (FIB) and Scanning Electron Microscope (SEM) system designed for Carl Zeiss. This particular project had specific noise level requirements and I'm pleased to say that the design came in *significantly* under those requirements. The design is now in production and doing well. Besides my FPGA work, I have also used both Altera and Xilinx SoCs, which may be applicable for your specific project. I would love the opportunity to discuss this further with you so we can get a good feel for how each other works and determine some of the time frame and design constraints. You may reach me through Freelancer chat or through Skype. My username there is "akohlsmith". I am looking forward to hearing from you! Regards, Andrew
$83 USD w 60 dni
0,0 (0 opinii)
0,0
0,0

O kliencie

Flaga PAKISTAN
Haripur, Pakistan
0,0
0
Zweryfikowana metoda płatności
Członek od lis 17, 2017

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