System Verilog ALU/Microprocessor

Dear customer, I am really happy to help you out of this project. I would like to introduce that I am an freelancer with 100% JOB COMPLETED in VHDL/VERILOG and about 200 JOB completed. I am really suitable for job description: First: I am an Electronics engineer who is very expertise with VHDL/Verilog. In fact, I have done with very high difficult project in backend design in FPGA by correct timinig closure for FPGA with 400 Mhz in Virtex Ultrascale+ in some field like mining coin (bitcore, and lyra2rev3) Also, I am very good in English (IELTS 6.0) and I have several year of researching so I can fully understand your requirement and understand fully about the papers and write the academic report. Please contact me and let me know if you want any special requirement and do with lower price. Thank you.

Hello. I am Digital design engineer with +6 years of experience in RTL coding in Verilog/System Verilog. I have wrote CPU (including ALU) following ISA/Opcode guidelines many times before. Therefore, I am the best to help based on my experience. May we discuss? Regards.

VERILOG EXPERT 15YRS EXPERIENCE HELLO, After KEENLY reading your description and being in possession of all CLEARLY STATED REQUIRED SKILLS as this is my area of PROFESSIONAL SPECIALIZATION for over 15 yrs. I hereby humbly request you to consider my bid for quality and professional work. Kindly hire me for a quality task. Thank-you!

Hi there, Can I get more details over chat? I would like to show you my FPGA projects that I did using VHDL coding. It also involved implementing OPCODES and showing the output on FPGA 7-segment displays. Looking forward to discussing this with you. Thank you. Regards, Ansar