TCP/IP Protocol with CYCLONE IV FPGA

hiii, I am a FPGA developper,i have 4year experience in FPGA development. Please share your schematics and project requirement file. only TCP/IP.? you want to make a IP core. please contact me for further discussion

Hi Project Manager, I carefully read your project requirements and I understand that you want to design TCP/IP Protocol with CYCLONE IV FPGA. Yes I will design it for you. Come on chat for more discussions… Meet waqas javaid an Electrical Engineer (Electronics) have an ability to design this project with accurate quality. I have design different projects on FPGA using Verilog language and Xiling software. Some of techniques like FSM, up and down counter as well as FPGA Spartan 3A/AN clock is running on 50MHz frequency that is so fast that it is impossible for human eye to see change in value. So in order to see changing values I write code to slow down this clock so that change in value occurs at every 2 seconds. It’s my pleasure to work with you with the new experience. Thanks.

Hi, I am an electronics and communication engineer , with good hands-on experience with Verilog and protocols. I think my skillset match your requirements. Looking forward to getting connected. Regards Anjana B