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    Configuration eine G100 mit Freepbx Zakończone left

    Ich suche jemanden der mir eine funktionierende Verbindung zwischen einem Freepbx und einem Digium 1-Port T1/E1/SIP Gateway (G100) herstellen kann

    PHP Architektura oprogramowania
    $189 (Avg Bid)
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    Project for seshupower Zakończone left

    Hi seshupower, I am an experienced professional in verilog/VHDL design and working on spartan FPGA board since past 10 months. Kindly let me know if you have any freelancing work for me. Thank you

    Inżynieria elektryczna Elektronika Inżynieria Matlab i Mathematica Mikrokontroler
    $20 / hr (Avg Bid)
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    fpga Zakończone left

    I am looking for a freelancer to help me with my project. The skills required are FPGA, DSP, Software defined Radio , RF MODEM, Matlab , Communication, Waveform generate, , and Verilog / VHDL. I am happy to pay a fixed priced and my budget is $250 - $750 USD. I have not provided a detailed description and have not uploaded any files.

    Inżynieria elektryczna FPGA Matlab i Mathematica Verilog / VHDL
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    Modified MIPS pipelined processor in system verilog Zakończone left

    You will implement a subset of the pipelined MIPS architecture in system verilog. You will implement a functioning outline of the pipelined processor for a small set of instructions, including: decoding all the instructions you will encounter in this project, implementing most of the MIPS pipeline, correct implementation of arithmetic and logic operations, and implementing a hazard detection and avoidance unit for these instructions. You will implement a five-stage MIPS pipeline, which is the most common organization for MIPS : 1. Fetch 2. Decode 3. Execute 4. Memory 5. Writeback Your design should contain a program counter, a separate data and code memories, a register file, an ALU, and any other components needed, along with the instruction ...

    Verilog / VHDL
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    Spartan 6 ADC and SPWM generation and control Zakończone left

    VHDL/ Verilog code development for Spartan 6 Slx9 to control SPWM using ADC interface along with training for code uploading on board and testing

    Elektronika Inżynieria FPGA
    $119 (Avg Bid)
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    Design project Zakończone left

    I need a logo designed. I am looking for a new logo for my construction company. I am a residential and commercial framer.

    Projekty graficzne Projektowanie logo
    $59 (Avg Bid)
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    Write an Android application - Farmer Zakończone left

    Its Sample application for framer and buyer, some of part will be hide.

    Android Mobile App Development
    $16 (Avg Bid)
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    matlab Zakończone left

    I am looking for a freelancer to help me with my project. The skills required are Algorithm, FPGA, Matlab and Mathematica and Verilog / VHDL. I am happy to pay a fixed priced and my budget is R$750 - R$2250 BRL. I have not provided a detailed description and have not uploaded any files.

    Algorytmy FPGA Matlab i Mathematica Verilog / VHDL
    $143 - $428
    $143 - $428
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    Verilog Floating point multiplier, 16bits, with one pipelining level after significands multiplication Zakończone left

    I need a 16 bits floating point multiplier, with one pipeline level. I dont need a very complex circuit.. One as easy as it can be would be perfect. I would like a short description of the blocks too. I attached a flow graph for the multiplier.

    Inżynieria elektryczna Verilog / VHDL
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    verilog/ vhdl project Zakończone left

    I need help with verilog/ vhdl project. Please bid here if you can do it. Thanks a lot.

    Inżynieria elektryczna FPGA Mikrokontroler Verilog / VHDL
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    designing VerySimpleCPU Zakończone left

    ...asm in Sim folder. It tests every single instruction. It even tests some instructions under a few different conditions. After you run this program on your Verilog design, you should make sure that you see the "after =" values in the marked memory locations. Other locations do not change. A few locations may change although they should not change if your design is buggy. 4) When you run the simulator/assembler , it assembles your program for Verilog simulation as well. The Verilog version of the assembler output is in program.v, which is directly in Verilog syntax. 5) Copy program.v into VerilogTB folder. It is included from blram.v and programs the block RAM (memory) VerySim...

    Asembler Programowanie C
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    automata Zakończone left

    I am looking for a freelancer to help me with my project. The skills required are Finite Element Analysis, Haskell, Prolog and Verilog / VHDL. I am happy to pay a fixed priced and my budget is $250 - $750 USD. I have not provided a detailed description and have not uploaded any files.

    Analiza metodą elementów skończonych Haskell Prolog Verilog / VHDL
    $494 (Avg Bid)
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    Designing a Debug logic in Verilog Zakończone left

    Hi, I have a processor designed and now i need to design a debug logic for that processor in Verilog. You need to design registers for halt and run and when you get a halt signal from outside you need to halt the processor and when you get a Run signal from outside it should continue running. If you are interested i can provide you more details. Regards, Dinesh

    Verilog / VHDL
    $88 (Avg Bid)
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    reed solomon coding Zakończone left

    i need a simple reed solomon encoder and decoder (16 8) with verilog code and its simulation results

    Kodowanie Matlab i Mathematica Programowanie Verilog / VHDL
    $31 (Avg Bid)
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    Design and development of VHDL programming based 8 bit CPU Zakończone left

    I am looking for a freelancer to help me with my project. The skills required are Design, Programming, Software Development and Verilog / VHDL. I am happy to pay a fixed priced and my budget is ₹1000 - ₹1200 INR. I have not provided a detailed description and have not uploaded any files.

    Projektowanie Programowanie Tworzenie oprogramowania Verilog / VHDL
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    matlab Zakończone left

    I am looking for a freelancer to help me with my project. The skills required are Algorithm, FPGA, Matlab and Mathematica and Verilog / VHDL. I am happy to pay a fixed priced and my budget is $250 - $750 USD. I have not provided a detailed description and have not uploaded any files.

    Algorytmy FPGA Matlab i Mathematica Verilog / VHDL
    $479 (Avg Bid)
    $479 Średnia Oferta:
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    Write some Software Zakończone left

    We have a team to develop Applications using the skills MATLAB,VERILOG,VHDL and PHP

    $1 - $5 / hr
    $1 - $5 / hr
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    Recognised expert UX/UI Designer Zakończone left

    I'm looking for an UX designer who can help me get an overview of the processes that an UX designer goes through. I'm thinking of making a career change from software engineering to UX design and I really enjoy using Sketch to visualize any idea striking my mind! However, UX design is n...really enjoy using Sketch to visualize any idea striking my mind! However, UX design is not only about the visuals but mostly centered around the user so I would like to get in contact with someone who can guide me through the process of working on projects, show me some previous work for steps that must find place and moreover be there for me if I'm having any questions. I'm thinking of learning framer for prototyping as I have solid background in JS, .Net, Java and C Loo...

    App Design UI / User Interface
    $12 - $18 / hr
    $12 - $18 / hr
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    asm crypter Zakończone left

    I am looking for a freelancer to help me with my project. The skills required are C# Programming, C++ Programming, LabVIEW and Verilog / VHDL. I am happy to pay a fixed priced and my budget is R$750 - R$2250 BRL. I have not provided a detailed description and have not uploaded any files.

    Programowanie w C# Programowanie w C++ LabVIEW Verilog / VHDL
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    Verilog e FPGA Zakończone left

    Implementar um JOGO mais simples possível com apenas os leds na linguagem verilog ou vhdl... Pode ser o jogo de decorar as cores dos leds que piscam, ou campo minado com leds, qualquer jogo simples (sem gráficos VGA.. projeto super simples na linguagem verilog).

    FPGA Verilog / VHDL
    $20 (Avg Bid)
    $20 Średnia Oferta:
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    Electronics Design Engineer (Experienced with HDL Languages Preferred) Zakończone left

    Hello, I require one experienced Electronic Design Engineer to design some projects. You must have experienced in VHDL and Verilog languages. Only Experienced bidders will be accepted. Details will be given to the selected bidder. Happy Bidding

    Inżynieria elektryczna Elektronika Inżynieria Verilog / VHDL
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    Verilog-HDL Code using Modelism -- - Zakończone left

    Analyze, design, synthesize, and simulate logic circuits using Verilog-HDL and different widely-used tools such as ModelSim.

    Inżynieria elektryczna Elektronika FPGA Verilog / VHDL
    $71 (Avg Bid)
    $71 Średnia Oferta:
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    Asic design - verilog/HDL code (Report) Zakończone left

    I do have the block and codes.. Just need short report about it in shortest time.

    Elektronika FPGA Mikrokontroler Verilog / VHDL
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    Fused Multiplication Addition Unit for binary single precision floating point units Zakończone left

    I need Verilog code for fused multiply add unit for single precision floating point unit. The code needs to run on a Spartan 6 FPGA. I will run it here on Xilinx ISE.

    Verilog / VHDL
    $335 (Avg Bid)
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    TCP/IP HDL IP on Altera FPGA - open to bidding Zakończone left

    Do you have work on TCP/IP protocol implemented on Altera FPGA and worked with internet ? it is better wrote on verilog-HDL , thanks so much

    Przesyłanie Artykułów Inżynieria elektryczna Oprogramowanie wbudowane Mikrokontroler Verilog / VHDL
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    $157 Średnia Oferta:
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    Asic design - Verilog/HDL code -Design -- 2 Zakończone left

    Analyze, design, synthesize, and simulate logic circuits using Verilog-HDL and different widely-used tools such as ModelSim

    Verilog / VHDL
    $158 (Avg Bid)
    $158 Średnia Oferta:
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    Asic design - Verilog/HDL code -Design Zakończone left

    Analyze, design, synthesize, and simulate logic circuits using Verilog-HDL and different widely-used tools such as ModelSim

    Verilog / VHDL
    $555 (Avg Bid)
    $555 Średnia Oferta:
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    capsim Zakończone left

    I am looking for a freelancer to help me with my project. The skills required are Geology, Haskell, Lisp and Verilog / VHDL. I am happy to pay a fixed priced and my budget is $250 - $750 USD. I have not provided a detailed description and have not uploaded any files.

    Geologia Haskell Lisp Verilog / VHDL
    $250 - $750
    $250 - $750
    0 składanie ofert
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    TCP/IP HDL IP on Altera FPGA Zakończone left

    Do you have work on TCP/IP protocol implemented on Altera FPGA and worked with internet ? it is better wrote on verilog-HDL , thanks so much

    Przesyłanie Artykułów Inżynieria elektryczna Oprogramowanie wbudowane Mikrokontroler Verilog / VHDL
    $50 (Avg Bid)
    $50 Średnia Oferta:
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    Asic design - verilog/HDL code Zakończone left

    Analyze, design, synthesize, and simulate logic circuits using Verilog-HDL and different widely-used tools such as ModelSim.

    Elektronika FPGA Verilog / VHDL
    $174 (Avg Bid)
    $174 Średnia Oferta:
    19 składanie ofert
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    Verilog-HDL Code using Modelism -- - Zakończone left

    Analyze, design, synthesize, and simulate logic circuits using Verilog-HDL and different widely-used tools such as ModelSim.

    Inżynieria elektryczna Elektronika FPGA Verilog / VHDL
    $167 (Avg Bid)
    $167 Średnia Oferta:
    10 składanie ofert
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    Verilog-HDL Code using Modelism -- -- 2 Zakończone left

    Analyze, design, synthesize, and simulate logic circuits using Verilog-HDL and different widely-used tools such as ModelSim.

    Inżynieria elektryczna Elektronika Inżynieria Verilog / VHDL
    $190 (Avg Bid)
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    smart parking Zakończone left

    my project is about parking space , it has 8 parking avaliabe .. each park have a light .. if the light was green it means that the park is available, if it wasn't it turn to red. we want to do it in ( verilog) language and apply it on ( FPGA- board ) .. the final result should include the code and state diagram

    Architektura oprogramowania
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    Verilog-HDL Code using Modelism -- Zakończone left

    Analyze, design, synthesize, and simulate logic circuits using Verilog-HDL and different widely-used tools such as ModelSim.

    Inżynieria elektryczna Elektronika Inżynieria Verilog / VHDL
    $187 (Avg Bid)
    $187 Średnia Oferta:
    8 składanie ofert
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    Verilog-HDL Code using Modelism Zakończone left

    Analyze, design, synthesize, and simulate logic circuits using Verilog-HDL and different widely-used tools such as ModelSim.

    Mikrokontroler Verilog / VHDL
    $163 (Avg Bid)
    $163 Średnia Oferta:
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    Hire an Internet Researcher Zakończone left

    Description of analysis: Description of analysis: To collect 75nos of valid telephone numbers of the architect company data by taking the following steps: 1/ on find London architects, subject to them based or registered addresses in postcodes SW1-SW15, WC1, WC2, EC1-EC4, W1-W6, NW1, NW8, NW6, N1, E1, SE1, SE16, SE5; 2/ filter to the next list only those companies that have websites and confirm on their websites they work/design residential; 3/ go onto and filter onto the next list companies, subject to a company having minimum £10k net assets (this data is freely accessible) and paste onto the google spreadsheet made up of: 3.1/ 25nos companies which are established/registered between 2005-2008, 3.2/ 25nos companies which are established/registered between

    Badania Internetu
    $106 (Avg Bid)
    $106 Średnia Oferta:
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    Verilog 64 bit adder Zakończone left

    Need a 64 bit adder than can deal with signed numbers.

    Verilog / VHDL
    $73 (Avg Bid)
    $73 Średnia Oferta:
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    website Zakończone left

    I need a new website for my Letter Photography. I need you to design and build my online store so ppl can choose photos, place their order, pay and have the order sent to my framer. The website needs to allow customers to type in letters and numbers, then scroll through our matching photos selections. Thanks for your time. I hope you have a wonderful day.

    HTML Java PHP SQL Projektowanie stron www
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    Verilog and circuit design Zakończone left

    Need a vending machine circuit, for counting coins.

    Verilog / VHDL
    $66 (Avg Bid)
    $66 Średnia Oferta:
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    diseño digital en verilog Zakończone left

    necesito transmitir datos numericos entre la fpga nexys 3 y el pc, usando protocolo uart por medio del puerto serial uart, comunicacion asincrona, el proyecto requiere que se lea un numero en binario tomado desde los switchs que trae la tarjeta y muestre el valor ingresado en form...fpga nexys 3 y el pc, usando protocolo uart por medio del puerto serial uart, comunicacion asincrona, el proyecto requiere que se lea un numero en binario tomado desde los switchs que trae la tarjeta y muestre el valor ingresado en formato decimal en el lcd 7 segmentos, adicional a eso que esta información sea transmitida via puerto uart al computador. los entregarles son el codigo hecho en verilog,( make file, archivos.v ) ademas de brindar una breve explicacion del trabajo realizado. hay un p...

    Projektowanie cyfrowe Inżynieria elektryczna Elektronika FPGA Verilog / VHDL
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    (System Verilog) Full implementation of SHA-1 algorithm Zakończone left

    SystemVerilog Using Quartus, and ModelSim Need to design the entire sha1 module (Design the yellow box) *There are more files that I will provide

    Verilog / VHDL
    $250 (Avg Bid)
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    Need an embedded programmers that is familiar with the Parallella board (https://www.parallella.org/) Zakończone left

    ...*** Description: Implement a hw/sw project in Parallella board (). So it is necessary that you have worked on this specific board and the source code that you deliver must be designed and must be run on this board well. the project can be one of these: 1. implement SDN gps that incorporate support for multi-constellation operability, with inclusion of Galileo E1 and GLONASS L1 signals. it should use the PS, PL and also Epiphany parts of the parallella board efficiently 2. implement AES encryption algorithm in the parallella board. it should use the PS, PL and also Epiphany parts of the parallella board efficiently and get better performance than implemented on similar platforms (like raspberry pi or other single board computers or even if it's possible

    Projektowanie cyfrowe FPGA
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    I would like to hire a Verilog / VHDL Designer Zakończone left

    32 bit coprocessor floating point unit i have the program. only i want to remove the errors which are 12.

    Verilog / VHDL
    $22 - $182
    $22 - $182
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    Verilog / VHDL experenced required Zakończone left

    Details will be shared with winning bidder. I have the mulitple project. please bid.

    Verilog / VHDL
    $16 (Avg Bid)
    $16 Średnia Oferta:
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    verilog VHDL design Zakończone left

    simple computer/ verilog design

    Verilog / VHDL
    $115 (Avg Bid)
    $115 Średnia Oferta:
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    verilog code for fused multiply add unit in verilog and implementing it on bysys3 - open to bidding Zakończone left

    Minimum 8bit processor verilog code for fused multiply add unit in verilog and implementing it on bysys3 using xilinx vivado 15.1

    Elektronika Oprogramowanie wbudowane Mikrokontroler Projektowanie obwodów drukowanych (PCB) Verilog / VHDL
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    verilog code for fused multiply add unit in verilog and implementing it on bysys3 Zakończone left

    Minimum 8bit processor verilog code for fused multiply add unit in verilog and implementing it on bysys3 using xilinx vivado 15.1

    Elektronika Oprogramowanie wbudowane Mikrokontroler Projektowanie obwodów drukowanych (PCB) Verilog / VHDL
    $250 (Avg Bid)
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    FPGA verilog 5 Zakończone left

    Looking for expert in verilog and fpga

    Verilog / VHDL
    $438 (Avg Bid)
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    Simple COmputer Assembly Language Programming. Zakończone left

    The Simple Computer from Chapter 8 of the textbook is a single‐cycle, load‐store central processing unit (CPU). The singlecycle Simple Computer illustrates many of the major principles and design constraints involved in implementing a CPU. For this project, you will write a small program to process the values stored in an array in the data memor...Chapter 8 of the textbook is a single‐cycle, load‐store central processing unit (CPU). The singlecycle Simple Computer illustrates many of the major principles and design constraints involved in implementing a CPU. For this project, you will write a small program to process the values stored in an array in the data memory. You will verify the operation of your program on the Simple Computer in a Verilog simulation and on the DE0 Nano ...

    Verilog / VHDL
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    Renovation/construction Zakończone left

    Looking for framer, drywaller, mudding and taping. Full gut renovation job on Danforth

    Złota rączka
    $2182 (Avg Bid)
    Lokalna
    $2182 Średnia Oferta:
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